TL3845 PDF

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Some of the internally implemented circuits are an undervoltage lockout UVLO , featuring a start-up current of less than 1 mA, and a precision reference trimmed for accuracy at the error amplifier input.

Other internal circuits include logic to ensure latched operation, a pulse-width modulation PWM comparator which also provides current-limit control , and a totem-pole output stage designed to source or sink high-peak current. Major differences between members of these series are the UVLO thresholds and maximum duty-cycle ranges. The corresponding typical thresholds for the TLx and TLx devices are 8. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Add the suffix R to the device type i. Pin numbers shown are for the D Package. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to the device GND terminal. The package thermal impedance is calculated in accordance with JESD TLx 0 —40 0 0 0 0 —0. NOTES: 4. Adjust VCC above the start threshold before setting it to 15 V. Output frequency equals oscillator frequency for the TLx and TLx Output frequency is one-half oscillator frequency for the TLx and TLx A ns Delay time to output ? These parameters are measured at the trip point of the latch, with VFB at 0 V.

Figure 1. Timing and bypass capacitors should be connected close to the GND terminal in a single-point ground. The transistor and 5-k? REF RT 4. Error Amplifier Adjust 5 k? Either method causes the output of the PWM comparator to be high refer to block diagram. At this point, the reference turns off, allowing the SCR to reset. Shutdown ? Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. REF 0. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty.

Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

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